Chaitanya Mamatha Ananda | University of California, Riverside

PhD Student, University of California, Riverside

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I am a Ph.D. candidate at the Department of Computer Science & Engineering, University of California Riverside (UCR) where I am fortunate to be advised by Professor Rajiv Gupta.

          My interests lie in designing compiler optimization techniques, with a particular focus on creating better memory layouts and reducing binary sizes. In this journey, I have had the privilege of collaborating with Dr. Sriraman Tallam and his group from Google, where we work on tackling new and challenging problems in this domain.

news

May 01, 2026 Our paper, “DeduBB: Binary Code Size Reduction via Post-Link Basic Block De-duplication” has been accepted for presentation at the ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES ‘26)!
Sep 01, 2025 Excited to join the Compiler Optimization Team at Google, Sunnyvale as a Student Researcher!
Nov 04, 2024 Our paper, “PreFix: Optimizing the Performance of Heap-Intensive Applications” has been accepted for presentation at the International Symposium on Code Generation and Optimization (CGO’25).
Aug 21, 2024 Successfully passed my PhD candidacy exam! :sparkles: :smile:

selected publications

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    PreFix: Optimizing the Performance of Heap-Intensive Applications
    Chaitanya Mamatha Ananda , Rajiv Gupta , Sriraman Tallam , and 2 more authors
    In The IEEE/ACM International Conference on Code Generation and Optimization (CGO) , 2025
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  2. dedubb.jpg
    DeduBB: Binary Code Size Reduction via Post-Link Basic Block De-duplication
    Chaitanya Mamatha Ananda , Mahbod Afarin , Rajiv Gupta , and 3 more authors
    In ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) , 2026