cv
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Basics
| Name | Chaitanya Mamatha Ananda |
| Label | Ph.D. Candidate in Computer Science |
| cmama002@ucr.edu | |
| Phone | 951-907-8519 |
| Summary | My research interests lie in the areas of compiler optimization, machine learning and deep learning. My doctoral research has involved (i) building optimized memory layouts for heap segment in x86 binaries, (ii) devising techniques for reducing code size in x86/Arm binaries and (iii) AI-driven techniques for improving code layout. |
Education
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2022.09 - Present Ph.D. Candidate
University of California, Riverside
Computer Science
- Artificial Intelligence (2024 Winter)
- Introduction to Deep Learning (2023 Fall)
- Advanced Computer Architecture (2023 Spring)
- Advanced Operating Systems (2023 Winter)
- High Performance Computing (2022 Fall)
- Compiler Construction (2022 Fall)
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2017.08 - 2021.06
Work
- 2025.09 - 2026.05
Student Researcher
Google, Sunnyvale
Exploring AI-driven approaches for improving code layout optimization. Designing techniques to improve memory layout on warehouse scale workloads.
- 2023.06 - 2025.09
Graduate Research Assistant
University of California, Riverside
Conducted research to improve memory layouts. Designed techniques to reduce code size in binaries.
- 2021.01 - 2021.06
Project Trainee
Robert Bosch Engineering and Business Solutions (RBEI), Bengaluru, India
Developed scripts to synchronize video and radar data from automated test driving.
- 2019.01 - 2022.12
Research Intern
Indian Institute of Science, Bengaluru, India
Developed a parallel programming model for solving partial differential equations using Regent/Legion. Designed an anomaly detector for scientific data using statistical and neural network based methods.
Projects
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PreFix
Developed PreFix, a novel optimization technique for heap-intensive applications that achieves near perfect separation of hot objects, improving spatial locality and application performance. PreFix employs profiling-guided hot object identification, preallocated memory regions, and object recycling, resulting in an average execution time reduction of 21.7% (up to 74%), significantly outperforming existing solutions like HDS and HALO. [CGO '25]
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DeduBB
Developed a framework for reducing the size of production binaries on x86 and Arm architectures at the post-link stage. [LCTES '26]
Publications
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2026.06.01 DeduBB: Binary Code Size Reduction via Post-Link Basic Block De-duplication
ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Chaitanya Mamatha Ananda, Mahbod Afarin, Rajiv Gupta, Sriraman Tallam, Han Shen and Xinliang David Li.
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2025.03.01 PreFix: Optimizing the Performance of Heap-Intensive Applications
The IEEE/ACM International Conference on Code Generation and Optimization (CGO)
Chaitanya Mamatha Ananda, Rajiv Gupta, Sriraman Tallam, Han Shen and Xinliang David Li.
Skills
| Programming | |
| Python | |
| C/C++ |
| Frameworks | |
| LLVM (BOLT) |
| Tools | |
| Vim | |
| Linux/Unix | |
| Git |
Awards
- 2022.09.01
Dean's Distinguished Fellowship
University of California, Riverside
- 2011.01.01
Inspire Award
Department of Science and Technology, Government of India